Friday, March 5, 2010

Memory Barriers article published by InfoQ

InfoQ has published an article I wrote about memory barriers and the JVM. Here's an excerpt:

"A trip to main memory costs hundreds of clock cycles on commodity hardware. Processors use caching to decrease the costs of memory latency by orders of magnitude. These caches re-order pending memory operations for the sake of performance. In other words, the reads and writes of a program are not necessarily performed in the order in which they are given to the processor. When data is immutable and/or confined to the scope of one thread these optimizations are harmless. Combining these optimizations with symmetric multi-processing and shared mutable state on the other hand can be a nightmare. A program can behave non-deterministically when memory operations on shared mutable state are re-ordered. It is possible for a thread to write values that become visible to another thread in ways that are inconsistent with the order in which they were written. A properly placed memory barrier prevents this problem by forcing the processor to serialize pending memory operations."

You can read the rest over at InfoQ ...

1 comment:

Ryan Eccles said...

Very interesting article. Unfortunately this isn't as well known as it probably should be.